Process variation analysis of 10T SRAM cell for low power, high speed cache memory for IoT applications

Govind Prasad, Dulari Tandon, Isha, Bipin Chandra Mandi, Maifuz Ali

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

SRAM (static random access memory) based cache memories are widely used due to their high speed. On-chip SRAMs are considered as one central part of the SOCs (system on chips) circuits as they determine the power dissipation of SoCs and the speed of its operation. Hence, having a low-power SRAMs is very important. Due to the downsizing of CMOS (complementary metal-oxide-semiconductor), low power design has become the major challenge of modern chip designs to make the devices portable and compact. The significant zone of worry in today's technology regards to speed, power consumption, size, and reliability to accomplish better performance. In conventional 6T SRAM, power consumption is very high. Thus, to overcome the problems, researchers have reported many SRAM cells such as 8T, 9T, 10T, NC, etc. The study and comparison of a different SRAM cell based on various performance metrics is done. This paper explores the design and analysis of a new 10T SRAM cell which majorly focuses on optimizing power consumption, delay, and stability.

Original languageEnglish
Title of host publication2020 7th International Conference on Signal Processing and Integrated Networks, SPIN 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages891-895
Number of pages5
ISBN (Electronic)9781728154756
DOIs
StatePublished - Feb 2020
Externally publishedYes
Event7th International Conference on Signal Processing and Integrated Networks, SPIN 2020 - Noida, India
Duration: 27 Feb 202028 Feb 2020

Publication series

Name2020 7th International Conference on Signal Processing and Integrated Networks, SPIN 2020

Conference

Conference7th International Conference on Signal Processing and Integrated Networks, SPIN 2020
Country/TerritoryIndia
CityNoida
Period27/02/2028/02/20

Keywords

  • Cache Memory
  • High Speed
  • Process Analysis
  • SRAM Cell
  • Stability

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