A 0.9-V 96-μW digital hearing aid chip with heterogeneous Σ-Δ DAC

Sunyoung Kim, Namjun Cho, Seong Jun Song, Donghyun Kim, Kwanho Kim, Hoi Jun Yoo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A full chip implementation of a low-power digital hearing aid is reported. It is composed of preamplifier, Σ-Δ ADC, DSP and Σ-Δ DAC with low-power technique. The hardwired DSP has 6 parameters to reduce power consumption with high flexibility. The Σ-Δ DAC adopts heterogeneous frequency to reduce power consumption further. The proposed digital hearing aid chip achieves 79-dB peak SNR and dissipates 96-μW from a single 0.9-V supply. The core area is 2.7-mm2 in a 0.18-μm standard CMOS technology.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages55-56
Number of pages2
StatePublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 15 Jun 200617 Jun 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI
Period15/06/0617/06/06

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